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    Dharmanshu Patel
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    80286

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    80286

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    741 views12 pages

    80286

    Uploaded by

    Dharmanshu Patel
    80286

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 12

    80286

    Features of 80286
    24-bit address bus. Able to address 16MB of physical memory. 1GB of virtual memory. It has a MMU[memory management unit] It operates in 2 modes Real address mode Protected virtual address mode

    INTERNAL ARCHITECTURE OF 80286


    Register organisation of 80286 A)Eight 16-bit general purpose registers B)Four 16-bit segment registers C)Status & control registers D)Instruction pointer All the above same as 8086

    Additional fields available in 80286 flag register


    IOPL[I/O Privilege field]-bits D12&D13 NT[Nested task flag]-bit D14 PE[Protection enable]-bit D16 MP[Moniter processor extension]-bit D17 EM[Processor extension emulator]-bit D18 TS[Task switch]-bit D19

    BLOCK DIAGRAM OF 80286

    4 functional parts.
    1)Address unit 2)Bus unit 3)Instruction unit 4)Execution unit

    Functional parts
    ADDRESS UNIT
    The address unit calculates the physical address of instructions & data.The address computed by AU is handed over to BU.

    BUS UNIT
    It fetches instruction bytes from the memory.Instructions are fetched in advance[Instruction Pipelining].These fetched instructions are arranged in a 6-byte prefetch queue.

    Functional parts
    INSTRUCTION UNIT
    The 6-byte prefetch queue forwards the instructions arranged init to the IU.It accepts instructions from prefetch queue & an instruction decoder decodes them one by one.Decoded instructions are latched onto a decoded instruction queue.

    EXECUTION UNIT
    The o/p of the decoding circuit is given to EU which is responsible for executing the instructions received from the decoded instruction queue.ALU carries all the arithmetic & logic operations.

    2 modes
    Real mode
    In this mode 80286 act as a fast 8086 It addresses only 1MB of physical memory using A0-A19 20-bit physical address is formed like 8086 Contents of segment registers are used as segment base address When the 80286 is reset ,it always starts its execution in real address mode In real mode first 1kb of memory is reserved for interrupt vector table Addresses FFFF0H to FFFFFH are reserved for system initialization.

    PROTECTED VIRTUAL ADDRESS MODE(PVAM)


    Virtual memory does not exist physically but it is available in the system The procedure of fetching the chosen pgm. Segments or data from the secondary storage into the physical memory is called swapping So it can address 1GB

    Physical address calculation in PVAM


    It uses 16-bit content of a segment register as a selector to address a descriptor stored in physical memory The descriptor is a block of contiguous memory locations containing information of a segment Privilege levels prevent unauthorized accesses Maximum segment size will be of 64kb

    Segment descriptor cache registers


    Caching was introduced in 80286 to minimise the time required for fetching the frequently required descriptor from the main memory Caching is the maintaining of the most frequently required data for execution in a high speed memory called cache memory

    Local and global descriptor table


    A descriptor table is an array of 8k descriptors 8byte entry in the table 8k*8=64kb of memory GDT-global descriptor table contains global descriptors common to all the tasks LDT-local descriptor table contains descriptors specific to a particular task

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